ECE Seminar: Marrying Application-Level Opportunities with Algorithm-Hardware Co-Design Towards Ubiquitous Edge Intelligence

Abstract

The record-breaking performance of artificial intelligence (AI) algorithms, especially deep neural networks (DNNs), has motivated a growing demand for bringing powerful AI-powered intelligent functionalities onto edge devices, e.g., virtual reality/augmented reality (VR/AR) and medical devices, towards ubiquitous edge intelligence. However, the powerful performance of AI algorithms comes with much increased computational complexity and memory storage requirements, which stand at odds with the limited compute/storage resources on edge devices. Additionally, the stringent application-specific requirements, including real-time response (i.e., high throughput/ low latency), high energy efficiency, and small form factor, further aggravate the aforementioned gap.

In this talk, I will introduce a holistic solution from energy- and latency-efficient architectures, to chips, and to integrated systems to closing the above-mentioned gap to enable more extensive AI-powered edge intelligence. Excitingly, my work shares the same underlying design insight, which is to advocate simultaneously harmonizing dedicated algorithms and hardware architectures via algorithm-hardware co-design while leveraging application-level opportunities to minimize redundancy with processing pipeline and this boost the achievable efficiency.

First, I will introduce our algorithm-hardware co-design work, called SmartExchange, which trades higher-cost memory storage/access for lower cost computations to boost energy- and latency-efficiency. Motivated by the promising efficiency achieved by SmartExchange, we further validated its co-design architecture by designing an AI acceleration chip prototype, which minimizes both the chip are and control overhead. To demonstrate the real-world advantages of the above SmartExchange architecture and its chip prototype, we developed i-FlatCam, a first-of-its-kind real-time eye-tracking system towards next-generation VR/AR devices, where we leverage the application-level opportunities to reduce both spatial and temporal redundancy. After that, we went beyond to build a scaled-up eye-tracking system, called EyeCoD, which targets a more general eye-tracking solution at the cost of marginally increased chip are as compared with i-FlatCams. Finally, I will conclude my talk with exciting future directions.

Bio

Yang (Katie) Zhao is currently a postdoctoral fellow at Georgia Institute of Technology, and obtained her Ph.D. from Rice University in 2022. Her research expertise spans both computer architecture and domain-specific acceleration chip designs, with her research interest centering around enabling AI-powered intelligent functionalities on resource-constrained edge devices through a holistic solution from efficient architectures, to chips, and to integrated systems. Her research has led to over 20 publications (11 as the 1st/ co-1st author) in top-tier computer architecture and circuit design conferences/journals, including ISCA, VLSI, MICRO, HPCA, ICCAD, ICASSP, FPGA, TNNL, TCAD, TVLSI, etc. Her work has been selected for IEEE Micro's Top Picks of 2023 and won 1st place demonstration at the 32nd ACM SIGDA University Demonstration at CAD 2022 and she is a recipient of the 2020 Cadence Women in Technology Scholarship.