Prof. Ahmed Louri and his research team presented a paper : “Dynamic Error Mitigation in NoCs using Intelligent Prediction Techniques,” at the 49th IEEE/ACM International Symposium on Microarchitecture(IEEE/ACM Micro). This seminal paper on the use of machine learning in the design of next generation computer chips was sponsored by the National Science Foundation and tackles one of the most critical issues of the future of computing chips: chip reliability and error mitigations. The authors propose the utilization of machine-learning algorithms to predict faults efficiently in the system before they occur. Their work provides a solid and effective path for scaling future chips and mitigating the reliability challenge. IEEE/ACM Micro was held October 15-19 in Taipei, Taiwan and is the premier and flagship conference for computer architecture research.
For more details, visit http://hpcat.seas.gwu.edu.