ECE Dissertations

Graph is a natural representation for many real-world applications, such as road maps, protein-protein interaction network, and code graphs. The graph algorithms can help mine useful knowledge from the corresponding graphs, such as navigation on road map graphs, key connector protein identification from protein-protein interaction networks, and vulnerability detection from code graphs. Though the graph algorithms are insightful, two major challenges block them from being easily applied in reality. The first challenge is the heavy computation due to the graph algorithms' high time complexity and graphs' big data trend in terms of size and count. Together, they made the runtime of graph computation remarkably long. The second challenge comes when we apply graph computation to real applications, e.g., cybersecurity. We need to answer many critical questions, such as how to build a graph, how to formalize the research problem to a graph problem, and whether the graph solution works better than traditional solutions. 

In this dissertation, I will discuss my past study on addressing these two challenges. First, I will present my work on high-performance computing for graph algorithms, i.e., iSpan [SC’18] and Aquila [HPDC’20]. iSpan can efficiently compute large graphs (up to a billion vertex) on both shared-memory and distributed-memory systems. Aquila is an adaptive parallel computation framework that covers a wide range of different highly optimized graph connectivity algorithms. Then, I will focus on applying graph analytics and graph-based machine learning algorithms to cybersecurity applications, i.e., code vulnerability detection and network threat detection. BugGraph [AsiaCCS’21] represents the binary code as an attributed graph, and the problem is formalized to a graph similarity problem. BugGraph identified 140 vulnerabilities from six commercial firmware. Realizing that knowing the compilation provenance of a binary code is very helpful for further code analysis, I designed Vestige [ACNS’21], a new compilation provenance identification system for binary code. We find that a nested graph structure is a more accurate representation for many practical applications. Observing no existing GNNs can directly learn on such graph structure, we design NestedGNN, a novel graph neural network framework for nested graphs. Finally, I will conclude with a future outlook on the computation of graph algorithms and cybersecurity applications.

This dissertation presents the exploitation of gold nanohole arrays (NHAs) and similarly nanopillar arrays (NPAs) based plasmonic sensing platforms for both gas-phase and liquid-phase biosensing applications for diseases, such as cystic fibrosis (CF) and severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2). The development of platforms begins with investigating the working principle of localized surface plasmon resonance (LSPR), various configurations of periodic metallic nanostructures, and fabrication methods. Then surface functionalization, platform setup, and performance characterization were principally studied on NHA sensors. Meanwhile, two types of detectors (a spectrometer or a CMOS imaging device) have been employed to improve device discrimination ability and portability. Plasmonic sensing platforms were functionalized with a layer of metal-organic framework (MOF) or antibodies, depending on the types of target analytes. The sensing platform integrated with a MOF-coated NHA sensor demonstrated the capability of detecting various CF-related gas-phase biomarkers, such as acetaldehyde and methanol, at nearing nmol/mol (ppb) levels, even when water vapor presented in the testing samples. The sensing platform integrated with an antibodies-functionalized sensor exhibited the initial feasibility of detecting SARS-CoV-2 spike proteins in liquid-phase, at approximately ng/μL levels.

The proliferation of core counts in chip-multiprocessors (CMP) enables the extraordinary growth in computing power to harness parallelism. The most critical barrier toward exploiting the parallelism is the communication challenge. This signals the advent of a paradigm shift from computation-centric to communication-centric systems. Consequently, a high-performance, power-efficient Network-on-Chip (NoC) architecture is of great importance to current and future computing systems. This dissertation is to overcome multiple communication challenges facing future manycore computing systems. Specifically, we focused on four research tasks: (1) designing power and performance efficient NoC architectures, (2) applying machine learning techniques to NoC power management, (3) enabling flexibility in heterogeneous manycores, and (4) optimizing the data movement for chiplet-based computing systems.

First, the end of voltage scaling has made power consumption the primary focus in current chip designs. To reduce the power consumption, a variety of power-saving techniques have been deployed at both circuit and architectural levels. Without a careful design, however, these techniques can conversely jeopardize the system performance. We targeted managing the power consumption and performance together for on-chip communication. Specifically, we built simulation models to characterize the application behavior and identify the bottlenecks of deploying power-saving techniques. Leveraging the findings from our simulation studies, we designed a bypass routing mechanism to continue the packet transmission during the sporadic traffic. The proposed design exploits the full benefits of power-gating while circumventing its performance overhead.

Second, the design space for optimized NoCs has expanded significantly comprising a plethora of techniques. The simultaneous application of these techniques requires monitoring of a large number of system parameters, prediction of runtime application features, and decision to select the right mix of solutions. Manually designing rules and strategies to handle such a large design space is likely to require a substantial engineering effort and enormous resources. Machine learning techniques can be applied to automatically infer complex problems to meet the target objective. Given that, we developed a reinforcement learning (RL) approach in NoC architectures to selflean a control policy with the goal of maximizing the power reductions and performance improvements. The proposed RL automatically explores the dynamic interactions among power gating, dynamic voltage and frequency scaling, and system parameters, learn the critical system parameters contained in the router and cache, and eventually evolve the optimal power management policy. This study shows that machine learning techniques could guide us to new and better solutions in NoC power management. Despite the many benefits of machine learning, it is costly to implement the RL model in the hardware. We thus proposed a simple artificial neural network to approximate the state-action table required by the RL model.

Third, modern heterogeneous manycore architectures comprise a large collection of computing resources such as CPUs, GPUs, and accelerators. While the increased computational capability and diversity facilitate the concurrent execution of multiple applications, it puts a large burden on the on-chip communication fabric. To tackle the mentioned problem, we proposed a flexible NoC architecture, called Adapt-NoC, that can provide efficient communication support for concurrent application execution. Specifically, Adapt-NoC can dynamically allocate several disjoint regions of the NoC, called subNoCs, with different sizes and locations for various running applications. Each of the dynamically-allocated subNoC is capable of supporting a given topology such as a mesh, cmesh, torus, or tree, and thus satisfying different types of communication in terms of latency, bandwidth, power, and traffic patterns.

Lastly, advanced packaging technology, such as silicon interposer, has emerged as an alternative to sustain the performance scaling by integrating multiple smaller chiplets within a single package. The tightly integrated a variety of chiplets compose a large-scale computing system, offering substantial computing capability to harness both heterogeneity and parallelism. However, such computing capability can only be unleashed if the underlying interconnection network can provide the required bandwidth and latency. We explored the communication needs existing in chiplet-based computing systems such as heterogeneous manycore architectures and deep neural network accelerators. On the top of this understanding, we designed a flexible interconnection network that can be tailored in response to myriad communication needs. The proposed interconnection network takes advantage of the wiring resources in the silicon interposer, composing a set of networks to support both inter- and intra-chiplet communications