Prof. Louri and His Research Team Have Presented a Paper Titled: “Machine Learning Enabled Power-Aware Network-on-Chip Design,” at the Design Automation and Test Europe (DATE 2017)

Prof. Louri and his research team have presented a paper titled: “Machine Learning Enabled Power-Aware Network-on-Chip Design,” at the Design Automation and Test Europe (DATE 2017), March 27 – 31, Lausanne, Switzerland.  DATE is one of the premier conferences on computer design with an acceptance rate of 20%. The paper tackles one of the major challenges for designing future computer systems, namely excessive power consumption. The research team exploits advances in machine learning algorithms to predict power consumption in such a way that power savings and performance are maximized.